IGBTs employing a weak collector are well known. Such devices, using a non-punch through technology, and using ultra-thin float zone wafers rather than more expensive wafers with an epitaxially formed silicon layer for device junctions and buffer zones for example, are described in a paper 0-7803-3106-0/96; 1996 I.E.E.E., entitled NPT-IGBT-Optimizing for Manufacturability, in the names of Darryl Burns et al.
As described in that paper, high voltage nonpunch through IGBTs (NPT-IGBTs) offer reasonable on state voltages, high short-circuit ruggedness, and minimal turn-off losses without heavy metal or E-beam lifetime killing. In addition, they have reduced cost as compared to the more conventional epitaxial IGBT because they are fabricated on low-cost bulk (float zone) silicon substrates and do not use thick, expensive epitaxial layers. The final thickness of float zone wafers for non-punch through IGBTs ranges from 80 microns for 600 volt devices to 250 microns for 1700 volt devices. Even thinner wafers are needed for even lower breakdown voltage. Such wafers are fragile and subject to breakage during processing. Typically, the wafer will be about 80 microns thick for a 600 volt breakdown and 185 microns thick for a 1200 volt breakdown.
The known NPT-IGBT uses a simple, shallow low concentration backside P type implant (a "weak" or "transparent" collector) to form an emitter with low efficiency, thereby providing fast turn-off time. (In contrast, the conventional epitaxial IGBT uses an N.sup.+ epitaxial buffer layer and lifetime killing to obtain fast turn-off time.) A collector contact including a first aluminum layer is then sintered into the bottom of the silicon wafer. A post metal deposition anneal is then needed to enable interaction (activation) between the aluminum and the backside silicon.
This subsequent anneal after metallizing to activate the junction requires repeated handling of the ultra-thin wafers, and wafer breakage can occur during these process steps despite great care in the wafer handling.
It is desirable to reduce the number of times the wafer must be handled during its processing to reduce the loss of wafers during the manufacturing process.